A ferroelectric random access memory (FeRAM) is used as a non-volatile semiconductor memory. The structures of ferroelectric capacitors provided in a ferroelectric memory are broadly classified into the stack structure and the planar structure, and it is ferroelectric capacitors of planar structure that are mass-produced today.
In contrast, from requests for higher packing densities, it is demanded that capacitors of stack construction capable of reducing the cell area be put to practical use. In the stack structure, immediately under a bottom electrode of a ferroelectric capacitor there is provided a contact plug to ensure conduction with a substrate (a diffusion layer). As disclosed in the Japanese Patent Application Laid-Open No. 2001-44376, tungsten or polysilicon is generally used as the material for this contact plug. The contact resistance of a W plug is usually 2 to 3 Ω, whereas the contact resistance of a plug formed from polysilicon is 1 to 2 kΩ.
A ferroelectric memory is often mounted together with a logic circuit. For example, a security-related chip that requires certification and an IC card are examples. In a logic circuit, usually a W plug is used. Therefore, also in a simulation performed in designing a logic circuit, the resistance value of a W plug is used as a parameter.
Therefore, to use equipment and techniques that have hitherto been used and to suppress an increase in the number of development steps and in cost, it is desirable to use a W plug as in the past in a logic part of a ferroelectric memory that is to be mounted together with a logic circuit.
Usually, in forming a ferroelectric capacitor, various kinds of heat treatment, such as crystallization annealing and recovery annealing, are necessary for obtaining good characteristics. For example, crystallization annealing is RTA (rapid thermal annealing) at 750° C. for 60 seconds and recovery annealing is furnace annealing at 650° C. for 60 minutes.
However, a W plug has the property of oxidizing at a very high speed and at a low temperature. When oxidation occurs in a part of a W plug once, the oxidation spreads over the whole plug. Therefore, contact defects are apt to occur and yields are apt to decrease. In order to suppress the oxidation of a W plug, it is desirable to lower the annealing temperature.
Thus, various kinds of annealing are required in order to improve the performance of a ferroelectric capacitor, whereas it is necessary to lower the annealing temperature to a somewhat low level in order to prevent an increase in the contact resistance of a W plug immediately under the capacitor. That is, under present circumstances, the performance of a ferroelectric capacitor and the contact performance of a W plug are in a trade-of relation.
Conventionally, after the formation of a ferroelectric capacitor, a contact hole between a bit line of a ferroelectric memory and a substrate is formed by performing etching once. The reason why a contact hole is formed after the formation of a ferroelectric capacitor is that in a case where a contact hole is formed before the formation of a ferroelectric capacitor and a W plug is embedded, the W plug may be oxidized during the formation of the ferroelectric capacitor.
However, when scaling down is promoted in the future, the aspect ratio of a contact hole increases, with the result that etching during the formation of a contact hole, embedding a glue film in a contact hole and the like become difficult.
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2001-44376
[Patent Document 2]
Japanese Patent Application Laid-Open No. 4-323821
[Patent Document 3]
Japanese Patent Application Laid-Open No. 11-133457